Continued physical scaling of mainstream silicon CMOS (Complementary Metal Oxide Semiconductor) and MOSFET (Metal Oxide Semiconductor Field effect transistor) technology in general has boosted the performance of the silicon devices in the last 40 years. However, even the benefits of the recently introduced new materials like high-k dielectrics and metal gates cannot guarantee that the race towards smaller devices will still be sustainable in terms of performance enhancement beyond the 22 nm node.
A possible solution, at least for the next technology nodes, could be the introduction of new channel materials with higher carrier mobility. Germanium and III-V compounds such as InSb, InAs, Ge and InGaAs with high electron mobility are very promising materials and possible solutions for CMOS devices beyond 22 nm.
Development of the III-V compound CMOS devices have been suffering from the Fermi level pinning (FLP) issues for the last four decades. FLP issue, suspected arising from the very high interfacial trap density of III-V compound interface with the gate dielectric, is one of the key showstoppers to refrain III-V CMOS from replacing the conventional Si CMOS. Currently, there are many ways suggested to avoid FLP including chalcogenide passivation, silicon passivation, and the like. The most popular state of the art technique is the use (deposition) of an interfacial passivation layer (IPL) e.g. Si or Ge in between the high mobility III-V compound semiconductor and the gate dielectric layer. Introduction of an IPL has however many unwanted effects such as a significant reduction in electron mobility of the channel. The physical thickness of interfacial passivation layer inevitably adds extra EOT to the gate stack and has a negative impact to the channel scaling budget (EOT<0.8 nm at 16 nm node). Furthermore, the diffusion of Si or Ge into III-V substrate under high temperature process such as implant activation anneals (>650 C) can alter the substrate doping significantly. Finally, the application of more than several nanometers of IPL material (Si or Ge, with 400 cm2/eV and 1900 cm2/eV electron mobility respectively) will likely degrade the high carrier mobility of the substrate (8000 cm2/eV for In0.53Ga0.47As).
It is a consensus of the industry to date that the optimal removal of FLP in a III-V CMOS device has not yet been achieved and there is still a need for methods which reduce or avoid the Fermi level pinning and at the same time enhances the device performance.